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| | <center>RO</center> | | | <center>RO</center> | ||
| | Parent Address | | | Parent Address | ||
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+ | |- | ||
+ | | | <div align="left">'''45'''</div> | ||
+ | | colspan="2" | PREFERRED | ||
+ | | | | ||
+ | | | <center>RW</center> | ||
+ | | | Preferred Parent Address | ||
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Revision as of 14:02, 24 October 2014
Contents |
Registers
Register are segmented following the OSI layers, so register map has a Start and an End.
Back to Data_Registers.
Start
| End
| Layer
| Remarks
|
---|---|---|---|
0
| 0
| NONE | Error register |
1
| 7
| PHY | Diagnostics and settings from/to HW |
8
| 39
| MAC | Diagnostics, commands or events from MAC Layer |
40
| 47
| NET | Diagnostics, commands or events from NET Layer |
48
| 63
| NAP | Network-to-Application |
64
| 511
| APP | Application (custom) |
Registers Attributes
Registers has several attributes:
- [R]ead, register can be read;
- [W]rite, register can be written;
- [E]vent, register is sent once;
- [O]nly, with [R,W,E] indicates unique option.
In other words, RO means “Read Only”, while RW means “Read & Write”.
PHY Registers (0..7)
Reg#
| | | | Description | |
---|---|---|---|---|---|
HI | LO | ||||
0
| ERR | | Error cause | ||
1
| RST | | Reset/Restart cause | ||
2
| CLASS | | Unique Device Class / Manufacturer0xFFFF: Undefined / Proprietary | ||
3
| TYPE | | Unique Device Type0xFFFF: Undefined / Proprietary | ||
4
| RODATA | | 48 bytes ROM vector data | ||
5
| COMMAND | | Bit Mapped (1/0): BIT0 → Force Update (write) Flash Memory BIT1 → Test mode set (nodes only) Write 0x0000 to stop commands. | ||
6
| SIGNATURE | | Device signature vector. Contains calibration data, so may differ from device to device. |
MAC Registers (8..39)
Reg# | | | | Description | |
---|---|---|---|---|---|
HI | LO | ||||
8
| X_OSC | | | Signed, Oscillator trim value | |
9
| TRIM_DATA | | Reserved | ||
10
| DEV | INDEX | | Index of last channel used (unsigned char) and deviation (signed char) | |
11
| RSSI | | | Signed, RSSI of last received frame | |
12
| UPTIME_LO | | | Time elapsed from last restart | |
13
| UPTIME_HI | ||||
14
| IDLE_LO | | | Time spent in IDLE | |
15
| IDLE_HI | ||||
16
| WAKE_LO | | | Time spent in WAKE | |
17
| WAKE_HI | ||||
18
| RX_LO | | | Time spent in RX | |
19
| RX_HI | ||||
20
| TX_LO | | | Time spent in TX | |
21
| TX_HI | ||||
22
| NOSYNCT_LO | | Count of TX frames in “no sync” state | ||
23
| NOSYNCT_HI | ||||
24
| SYNCT_LO | | Count of TX frames in “sync” state | ||
25
| SYNCT_HI | ||||
26
| SYNCR_LO | | Count of RX frames in “sync” state | ||
27
| SYNCR_HI | ||||
28
| NOISE | CHAN | | Vector of noise floor on used channels. NOISE is expressed in [dB] (signed char). |
NET Registers (40..47)
Reg# | | | | Description | |
---|---|---|---|---|---|
HI | LO | ||||
40
| NETWORK_KEY_0 | | Network Key 0 | ||
41
| NETWORK_KEY_1 | | Network Key 1 | ||
42
| NETWORK_KEY_2 | | Network Key 2 | ||
43
| NETWORK_KEY_3 | | Network Key 3 | ||
44
| ADDRESS | | Address in the network | ||
45
| PARENT | | Parent Address | ||
45
| PREFERRED | | Preferred Parent Address |
WINE Application Registers (48..63)
Reg# | | | | Description | |
---|---|---|---|---|---|
HI | LO | ||||
48
| VERSION | | WINE software version | ||
49
| INFO | | Bit Mapped (1/0): BIT0 → Routing capabilities Yes/No BIT1 → Base Station Yes/No BIT2 → Anchor Yes/No BIT[3..7] → Localization request count BIT8 → Restart BIT9 → Trimmed | ||
50
| SURVIVAL | | | Survival time | |
51
| CHILD_LOST | | Address of lost cluster child node | ||
52
| ENROLL_MODE | | Bit Mapped (1/0): BIT0 → Enroll Enabled Yes/No BIT1 → Enroll Batch/Single | ||
53
| ENROLL_ADDR | | Address of next enrolling node | ||
54
| ELP | | Extreme Low Power Parameters: BIT[0..9] → slot modulation value [node slots] BIT[10..15] → interaction timeout [node slots] | ||
55
| ANCHOR_LEVEL | | Anchor level (0 → no anchor) | ||
56
| LATITUDE_H | | | Latitude high part, expressed as signed 16 bits ['] | |
57
| LATITUDE_L | | | Latitude low part, expressed as signed 16 bits [“/100] | |
58
| LONGITUDE_H | | | Longitude high part, expressed as signed 16 bits ['] | |
59
| LONGITUDE_L | | | Longitude low part, expressed as signed 16 bits [“/100] | |
60
| ALTITUDE | | | Altitude expressed as signed 16 bits [m] | |
61
| LOCALIZE | | Localization request (count) trigger or address of localization data source | ||
62
| PTP_DEST | | Point-To-Point data transfer link address | ||
63
| SPEED | CHAN | | Point-To-Point data transfer configuration |
APP Registers (64..447)
These registers start from number 64 up to 447, for a total of 384.
The register definition in this section depends on application, so description of these registers is out of the scope of this section.
RESERVED Registers (448..511)
These 64 registers are reserved to send “open data” from WINE base-station to nodes as:
- ACK payload, or...
- standard registers write.
These registers are RW from the BS point of view, but RO for nodes.
Reg# | | | | Description | |
---|---|---|---|---|---|
HI | LO | ||||
486
| DEV_NAME | | | Vector of mnemonic name of device (max. 24 characters / 12 words) | |
487
| INFO_BLOCK_0 | | | Information register block: BIT[0..4] → Block Length BIT[5..6] → Reserved BIT[7..15] →Register Start | |
488
| INFO_TIME_0 | | | Interval of INFO refresh | |
489
| INFO_BLOCK_1 | | | Information register block: BIT[0..4] → Block Length BIT[5..6] → Reserved BIT[7..15] →Register Start | |
490
| INFO_TIME_1 | | | Interval of INFO refresh | |
491
| INFO_BLOCK_2 | | | Information register block: BIT[0..4] → Block Length BIT[5..6] → Reserved BIT[7..15] →Register Start | |
492
| INFO_TIME_2 | | | Interval of INFO refresh | |
493
| INFO_BLOCK_3 | | | Information register block: BIT[0..4] → Block Length BIT[5..6] → Reserved BIT[7..15] →Register Start | |
494
| INFO_TIME_3 | | | Interval of INFO refresh | |
495
| ACK_SIZE | | Enables ACK Payload, setting the number of registers to send as ACK Payload. Ranges from 0 (no ACK Payload) to 16 (max payload size). | ||
496TO511
| ACK_PAYLOAD | | Open data. |
(*) Only BS can write.