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Common Registers

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= Registers = = Registers =
-<nowiki>Register are segmented following the OSI layers, so register map has a Start and an End. To the first three WINE layers (PHY, MAC, NET), 32 registers, 16 [bit] each, are reserved.</nowiki>+<nowiki>Register are segmented following the OSI layers, so register map has a Start and an End.
- +
-A hole has been reserved for Not Yet Defined WINE layers.+
- +
-Starting from 256 and up, registers are reserved to application.+
- +
{| style="border-spacing:0;" {| style="border-spacing:0;"

Revision as of 16:26, 15 September 2014

Contents

Registers

Register are segmented following the OSI layers, so register map has a Start and an End. {| style="border-spacing:0;" | colspan="2" style="border-top:0.05pt solid #000000;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''Registers''' | style="border-top:0.05pt solid #000000;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''Layer''' | style="border:0.05pt solid #000000;padding:0.097cm;"| '''Remarks''' |- | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''Start''' | style="border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| '''End''' |- | style="background-color:transparent;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">0</div> | style="background-color:transparent;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">0</div> | style="background-color:transparent;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| NONE | style="background-color:transparent;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Error register |- | style="background-color:#ff6633;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">1</div> | style="background-color:#ff6633;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">7</div> | style="background-color:#ff6633;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| PHY | style="background-color:#ff6633;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Diagnostics and settings from/to HW |- | style="background-color:#ff9966;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">8</div> | style="background-color:#ff9966;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">39</div> | style="background-color:#ff9966;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| MAC | style="background-color:#ff9966;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Diagnostics, commands or events from MAC Layer |- | style="background-color:#ffcc99;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">40</div> | style="background-color:#ffcc99;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">47</div> | style="background-color:#ffcc99;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| NET | style="background-color:#ffcc99;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Diagnostics, commands or events from NET Layer |- | style="background-color:#94bd5e;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">48</div> | style="background-color:#94bd5e;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">63</div> | style="background-color:#94bd5e;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| NAP | style="background-color:#94bd5e;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Network-to-Application |- | style="background-color:#94bd5e;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">64</div> | style="background-color:#94bd5e;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| <div align="right">511</div> | style="background-color:#94bd5e;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:none;padding:0.097cm;"| APP | style="background-color:#94bd5e;border-top:none;border-bottom:0.05pt solid #000000;border-left:0.05pt solid #000000;border-right:0.05pt solid #000000;padding:0.097cm;"| Application (custom) |} Registers has several attributes: * <nowiki>[R]ead, register can be read;

  • [W]rite, register can be written;
  • [E]vent, register is sent once;
  • [O]nly, with [R,W,E] indicates unique option.

In other words, RO means “Read Only”, while RW means “Read & Write”.

PHY Registers (0..7)

Reg#
WORD
Units
Mode
 Description
HI LO
0
 ERR
RO
 Error cause
1
 RST
RO
 Reset/Restart cause
2
 CLASS
RO
 Unique Device Class / Manufacturer0xFFFF: Undefined / Proprietary
3
 TYPE
RO
 Unique Device Type0xFFFF: Undefined / Proprietary
4
 RODATA
RO
 48 bytes ROM vector data
5
 COMMAND
WO
 Bit Mapped (1/0):BIT0: Force Update (write) Flash MemoryBIT1: Test mode set (nodes only)

Write 0x0000 to stop commands.

6
 SIGNATURE
RW
 Device signature vector. Contains calibration data, so may differ from device to device.

MAC Registers (8..39)

Reg#
WORD
Units
Mode
 Description
HI LO
8
 X_OSC
[Hz]
RO
 Signed, Oscillator trim value
9
 TRIM_DATA
RO
 Reserved
10
 DEV INDEX
RO
 Index of last channel used (unsigned char) and deviation (signed char)
11
 RSSI
dB
RO
 Signed, RSSI of last received frame
12
 UPTIME_LO
s
RO
 Time elapsed from last restart
13
 UPTIME_HI
14
 IDLE_LO
s/1024
RO
 Time spent in IDLE
15
 IDLE_HI
16
 WAKE_LO
s/1024
RO
 Time spent in WAKE
17
 WAKE_HI
18
 RX_LO
s/1024
RO
 Time spent in RX
19
 RX_HI
20
 TX_LO
s/1024
RO
 Time spent in TX
21
 TX_HI
22
 NOSYNCT_LO
RO
 Count of TX frames in “no sync” state
23
 NOSYNCT_HI
24
 SYNCT_LO
RO
 Count of TX frames in “sync” state
25
 SYNCT_HI
26
 SYNCR_LO
RO
 Count of RX frames in “sync” state
27
 SYNCR_HI
28
 NOISE CHAN
RO
 Vector of noise floor on used channels. NOISE is expressed in [dB] (signed char).

NET Registers (40..47)

Reg#
WORD
Units
Mode
 Description
HI LO
40
 NETWORK_KEY_0
RW
 Network Key 0
41
 NETWORK_KEY_1
RW
 Network Key 1
42
 NETWORK_KEY_2
RW
 Network Key 2
43
 NETWORK_KEY_3
RW
 Network Key 3
44
 ADDRESS
RW
 Address in the network
45
 PARENT
RO
 Parent Address

WINE Application Registers (48..63)

Reg#
WORD
Units
Mode
 Description
HI LO
48
 VERSION
RO
 WINE software version
49
 INFO
RO
 Bit Mapped (1/0):BIT0: Routing capabilities Yes/NoBIT1: Base Station Yes/NoBIT2: Anchor Yes/NoBIT[3..7]: Localization request countBIT8: RestartBIT9: Trimmed
50
 SURVIVAL
s
RW
 Survival time
51
 CHILD_LOST
EO
 Address of lost cluster child node
52
 ENROLL_MODE
RW
 Bit Mapped (1/0):BIT0: Enroll Enabled Yes/NoBIT1: Enroll Batch/Single
53
 ENROLL_ADDR
RW
 Address of next enrolling node
54
 ELP
WO
 Extreme Low Power Parameters:bit [0..9] → slot modulation value [node slots]bit [10..15] → interaction timeout [node slots]
55
 ANCHOR_LEVEL
RW
 Anchor level (0 → no anchor)
56
 LATITUDE_H
'
RW
 Latitude high part, expressed as signed 16 bits [']
57
 LATITUDE_L
“/100
RW
 Latitude low part, expressed as signed 16 bits [“/100]
58
 LONGITUDE_H
'
RW
 Longitude high part, expressed as signed 16 bits [']
59
 LONGITUDE_L
“/100
RW
 Longitude low part, expressed as signed 16 bits [“/100]
60
 ALTITUDE
m
RW
 Altitude expressed as signed 16 bits [']
61
 LOCALIZE
RW
 Localization request (count) trigger or address of localization data source
62
 PTP_DEST
RW
 Point-To-Point data transfer link address
63
 SPEED CHAN
RW
 Point-To-Point data transfer configuration

APP Registers (64..447)

These registers start from number 64 up to 447, for a total of 384.

The register definition in this section depends on application, so description of these registers is out of the scope of this document.

RESERVED Registers (448..511)

These 64 registers are reserved to send “open data” from WINE base-station to nodes as:

  • ACK payload, or...
  • standard registers write.

These registers are RW from the BS point of view, but RO for nodes.


Reg#
WORD
Units
Mode
 Description
HI LO
487
 INFO_BLOCK_0
[]
RW
 Information register block:BIT[0..4]: Block LengthBIT[5..6]: ReservedBIT[7..15]:Register Start
488
 INFO_TIME_0
[s]
RW
 Interval of INFO refresh
489
 INFO_BLOCK_1
[]
RW
 Information register block:BIT[0..4]: Block LengthBIT[5..6]: ReservedBIT[7..15]:Register Start
490
 INFO_TIME_1
[s]
RW
 Interval of INFO refresh
491
 INFO_BLOCK_2
[]
RW
 Information register block:BIT[0..4]: Block LengthBIT[5..6]: ReservedBIT[7..15]:Register Start
492
 INFO_TIME_2
[s]
RW
 Interval of INFO refresh
493
 INFO_BLOCK_3
[]
RW
 Information register block:BIT[0..4]: Block LengthBIT[5..6]: ReservedBIT[7..15]:Register Start
494
 INFO_TIME_3
[s]
RW
 Interval of INFO refresh
495
 ACK_SIZE
RW*
 Enables ACK Payload, setting the number of registers to send as ACK Payload. Ranges from 0 (no ACK Payload) to 16 (max payload size).
496TO511
 ACK_PAYLOAD
RW*
 Open data.

(*) Only BS can write.

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